AS 2805.5.2:2009 Electronic funds transfer— Requirements for interfaces
5 Requirements
For some of the described modes, padding of the plaintext variables may be required. Padding techniques, although important from a security perspective, are not within the scope of this In- ternational Standard, and throughout this standard it is assumed that any padding, as necessary, has already occurred.
NOTE Advice on the selection of a padding method for use with the CBC mode of operation is provided in Annex B.2.3.
For the Cipher Block Chaining (CBC) mode of operation (see clause 7), one parameter m needs to be selected. For the Cipher Feedback (CFB) mode of operation (see clause 8), three parameters r, j and k need to be selected. For the Output Feedback (OFB) mode of operation (see clause 9) and the Counter (CTR) mode of operation (see clause 10), one parameter j needs to be selected. When one of these modes of operation is used the same parameter value(s) need to be chosen and used by all communicating parties. These parameters need not be kept secret.
All modes of operation specified in this International Standard require the parties encrypting and decrypting a data string to share a secret key K for the block cipher in use. All modes of operation apart from the Electronic Codebook (ECB) mode also require the parties to share a starting variable SV, where the length of SV will depend on the mode in use. The value of the starting variable should normally be different for every data string encrypted using a particular key (see also Annex B). How keys and starting variables are managed and distributed is outside the scope of this International Standard.
7.1 Preliminaries
The CBC mode of operation is defined by an interleave parameter m > 0, the number of ciphertext blocks that must be stored whilst processing the mode. The value of m should be small (typically m = 1) and at most 1024.
NOTE The choice of 1024 as the upper limit for m is somewhat arbitrary. It is intended to provide a realistic upper bound on the number of hardware processors.